A logic analyzer is a test and measurement instrument that is extremely useful for troubleshooting digital circuits involving numerous signals. Like an oscilloscope, a logic analyzer captures signals from a Device Under Test (DUT) and displays a representation of those signals on a display screen. Unlike an oscilloscope, which typically has up to four input channels, a logic analyzer may have 32, 64, 128 or more input channels. Oscilloscopes acquire signal data representative of analog characteristics of the signal, such as specific amplitude values, rise times, fall times, etc. A logic analyzer is concerned with logic levels (0 and 1) and timing relationships between the signals.
Meanwhile, double data rate (DDR) random access memories (RAMs) are increasingly employed in a variety of electronics systems and, in particular, in computer systems. FIG. 1 illustrates an example of a memory array 10 of a DDR RAM 5. DDR RAM 5 has a multi-bank architecture with a plurality of memory cells organized in banks 12, rows 14 and columns 16 of bits 11. DDR RAM 5 also includes row buffers 18. A typical DDR RAM 5 may have: four to eight banks 12; 16K rows 14 per bank 12; 1024 columns 16 per row 14; and four to sixteen memory bits 11 per column.
An example execution of a memory access Transaction for DDR RAM 5 will be described with respect to FIG. 2. For a single read or write Transaction, only one bank 12 of the DDR RAM is accessed. As shown in FIG. 3, the requested row 14 is activated and copied to a row buffer 18 of the corresponding bank 12. Then read and/or write bursts are issued to the active row 14. Finally, the row 14 is precharged and the data is stored back into the memory array 10.
A logic analyzer is a useful instrument for debugging DDR RAM devices, analyzing their performance, verifying their compliance with published specifications, etc.
However, data records acquired by a logic analyzer can be very long, for example, tens of megasamples on each channel of the logic analyzer. While the ability to capture such a large amount of data is certainly a desirable feature for a logic analyzer, identifying and organizing specific data within a long data record is often a daunting task for a user. For example, a user may want to view data pertaining to related events on one screen without having to scroll through different sets of data that were captured at different times and/or switching from one display screen to another.
In particular, in the case of a DDR RAM device, a traditional logic analyzer display may show decoded Transactions at various locations in a display window in time-stamp order. This means that interrelated Transactions may be spread out through multiple locations in the display and all of the interrelated Transactions would not necessarily be shown with each other in a single display screen and be separated by several pages in the display. That is, a user typically must scroll through the window to find all of the individual decoded Transactions which are related to each other, and cannot see them all at once, or even easily identify related Transactions. In fact, in a DDR RAM data capture, different Transactions for different ranks and banks of the DDR RAM device which is being analyzed may be interleaved with each other, thus making it even harder for a user to track related Transactions. Furthermore, doing so manually can be a tedious task.
Accordingly, it would be desirable to be able to provide a logic analyzer instrument and method which can display captured DDR RAM data in a manner that may be more easily understood by a user.